In this project, we design and demonstrate a heterogeneous CMOS transceiver with silicon photonic chips for future multiple Gb/s radio-over-fiber communication systems as shown in Figure 1(a). Its high throughput, low latency characteristics make it suitable for real-time applications such as virtual reality and video streaming. The overall block diagram is shown in Figure 1(b). Critical blocks include photonic modulator, photodiode, coupler, multiplexer, receiver, transmitter, and antenna. In CMOS transceiver, we propose novel circuit design of low-noise amplifiers, power amplifiers, equalizers, etc.
For the transceiver, we design 28-GHz transimpedance amplifier, phase shifter, power amplifier, low-noise amplifier, modulator driver, variable-gain amplifier, all in 90-nm standard CMOS technology. Patch antennas are designed on a high-speed printed circuit board to be connected to the electronic chip using bondwires. Silicon photonic chip is as well connected to the CMOS chip through bondwires. Therefore, an accurate high frequency modeling of on-chip/on-board devices and interconnects of heterogeneous substrates are important. The photo of the transceiver is shown in Figure 2.

This work has been awarded in Future Tech Award, 2022.

High quality signal generation is critical to wired communications, wireless communications, radars, phased arrays, and so on. In CMOS technologies, as the operation frequency is close to or above the device cutoff frequencies, innovative circuit architectures and design techniques are required to develop a millimeter-wave or sub-terahertz signal source.
We aim to develop low phase noise, low power consumption oscillators , quadrature oscillators, and phase locked loops, in standard CMOs technologies. One example shown in Figure 1 is a 210-GHz oscillator, published in IEEE Transaction of Microwave Theory and Techniques, 2018.

We also develop 340-GHz signal source in 90-nm CMOS technology using high power amplifier, doublers, quadruplers, and all-pass filters where the operation frequency is over the device cutoff frequency. This signal source achieves a wide tuning range from 328 GHz to 352 GHz, with -10 dBm peak output power.  Block diagram and chip photo are shown in Figure 2.
Related topics are published in IEEE International Microwave Symposium, IEEE International Symposium of Circuits and Systems, IEEE Asian Solid-State Circuits Conference, IEEE Radio Frequency Integration Technology, etc.